The present invention relates to a technique for manufacturing a semiconductor integrated circuit device and, more particularly, to a technique which is effective when applied to a well separation technique, by which in order to electrically separate a well (semiconductor region) formed in a semiconductor substrate and the semiconductor substrate, another well is so formed in the bottom and side portions of the former well as to encompass the same.
This well separation technique enables a first well formed in a semiconductor substrate to be supplied with a desired voltage different from that applied to the semiconductor substrate, by electrically separating the first well from a second well formed therearound.
This technique is applied to a variety of semiconductor integrated circuit devices such as a DRAM (Dynamic Random Access Memory) in which a memory cell is formed in a first well, for example, to apply a back bias voltage to the MISxe2x80xa2FET (Metal Insulator Semiconductor Field Effect Transistor) of the memory cell, or a flash memory (EEPROM: Electrically Erasable Programmable ROM), in which a negative voltage is applied to the first well.
Here will be described a semiconductor integrated circuit device having a well separation structure examined by us.
At the well separation region in the semiconductor substrate of a second conductivity type, more specifically, there are formed a deep well of a first conductivity type and a shallow well of the second conductivity type which is formed in the region of the deep well. This deep well is formed by diffusing an impurity from the major surface to a deep position of the semiconductor substrate to encompass the outer periphery of the shallow well and to separate the shallow well and semiconductor substrate electrically. As a result, the shallow well can be fed with a voltage different from that to be applied to the semiconductor substrate.
In another region of the semiconductor substrate, there are formed an ordinary well of the first conductivity type and an ordinary well of the second conductivity type. These wells of the first conductivity type and the second conductivity type are formed by diffusing an impurity from the major surface to a predetermined position of the semiconductor substrate.
In the technique for forming the aforementioned well structure with two masks, the aforementioned well structure is realized with two masks: a common mask for an impurity introducing step to form the deep well of the first conductivity type and the ordinary well of the first conductivity type, and a common mask for an impurity introducing step to form the shallow well of the second conductivity type and the ordinary well of the second conductivity type.
In the technique thus far described for forming the two wells with one mask, however, the following problems have been found out by us.
Specifically, the first problem comes from the fact that the shallow well of the second conductivity type is formed by compensating the impurity of the second conductivity type and the impurity of the first conductivity type. That is, the effective impurity concentration of the second conductivity type increases to about two times as high as that of the second conductivity type in the ordinary well of the second conductivity type having no well separation, so that the transistor to be formed over the major surface of the semiconductor substrate has greatly different characteristics, especially the threshold voltage. A new mask is required to adjust the threshold voltage.
The second problem is that the total impurity concentration of the shallow well of the second conductivity type increases to about three times the impurity concentration of the ordinary well of the second conductivity type which is subjected to no well separation. As a result, the mobility of the carriers in the major surface region of the semiconductor substrate lowers to deteriorate the characteristics of the transistor to be formed over the major surface, especially to reduce the drain current.
The aforementioned two problems become serious as the factors obstructing the higher performance of the transistor as the well density has a tendency to rise more with the further miniaturization of the transistor.
An object of the invention is to provide a technique capable of optimizing the impurity concentrations of a well and an ordinary well in a well separation region without inviting any increase in the number of steps for manufacturing the semiconductor integrated circuit device.
Another object of the invention is to provide a technique capable of improving the characteristics of the elements to be formed in the well and the ordinary well in the well separation region without inviting any increase in the number of steps for manufacturing the semiconductor integrated circuit device.
The aforementioned and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the aspects of the invention to be disclosed herein will be briefly summarized in the following.
According to the invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming, by patterning, over a major surface of a semiconductor substrate a first mask through which a first well forming region and a second well forming region formed at a distance from the first well forming region are exposed;
(b) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a buried well region of a first conductivity type at a deep position of the semiconductor substrate in the first well forming region;
(c) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a shallow well region of a second conductivity type over the buried well region of the first conductivity type in the first well forming region and the well forming region;
(d) forming, by patterning, over the major surface of the semiconductor substrate a second mask through which a third well forming region encompassing the buried well region of the first conductivity type of the first well forming region, and the shallow well region of the second conductivity type and a fourth well forming region formed at a distance from the first well forming region; and
(e) doping the semiconductor substrate with an impurity by using the second mask as an impurity introduction mask so as to form a shallow well region of the first conductivity type encompassing the outer periphery of the shallow well region of the second conductivity type of the first well forming region and electrically connected with the buried well region of the first conductivity type of the first well forming region in the third well forming region and to form a shallow well region of the first conductivity type in the fourth well forming region,
wherein in the first well forming region, the shallow well region of the second conductivity type in the first well forming region is encompassed by the shallow well region of the first conductivity type formed in the third well forming region and the buried well region of the first conductivity type in the first well forming region and is electrically separated from the semiconductor substrate,
wherein in the second well forming region, the shallow well region of the second conductivity type is electrically connected with the semiconductor substrate.
In the invention, moreover, the impurity introduction of the step (e) is so performed that the impurity concentration of at least a portion of the shallow well region of the first conductivity type in the third well forming region is higher than that of the shallow well region of the second conductivity type in the first well forming region.
Moreover, the invention further comprises the steps of:
forming, by patterning, over a major surface of a semiconductor substrate a third mask through which a fifth well forming region formed at a distance from the first well forming region is exposed;
doping the semiconductor substrate with an impurity by using the third mask as an impurity introduction mask so as to form a shallow well region of the first conductivity type in the fifth well forming region;
forming, by patterning, over the major surface of the semiconductor substrate a fourth mask through which a sixth well forming region planarly encompassed by the fifth well forming region is exposed;
doping the semiconductor substrate with an impurity by using the fourth mask as an impurity introduction mask so as to form a shallow well region of the second conductivity type in the sixth well forming region;
forming, by patterning, over the major surface of the semiconductor substrate a fifth mask through which exposed are fifth well forming region, the sixth well forming region and a portion of the element separation region encompassing the fifth well forming region and which has its opening end provided over the element separation region; and
doping the semiconductor substrate with an impurity by using the fifth mask as an impurity introduction mask so as to form a buried well region of the first conductivity type under the shallow well region of the first conductivity type of the fifth well forming region and the shallow well region of the second conductivity type of the sixth well forming region such that the buried well region is electrically connected with the shallow well regions of the first conductivity type of the fifth well forming region and the sixth well forming region and extends below a portion of the element separation region encompassing the fifth well forming region,
wherein in the sixth well forming region, the shallow well region of the second conductivity type in the sixth well forming region is encompassed by the shallow well region of the first conductivity type of the fifth well forming region and the buried well regions of the first conductivity type of the fifth well forming region and the sixth well forming region and electrically separated from the semiconductor substrate.
Moreover, the invention further comprises the steps of:
in the first well forming region, forming over the major surface of the semiconductor substrate a sixth mask through which the shallow well region of the first conductivity type is exposed; and
doping the first well forming region with an impurity by using the sixth mask as an impurity introduction mask so as to override the conductivity type of the shallow well region of the second conductivity type in the first well forming region and to form a shallow well region of the first conductivity type in the first well forming region,
wherein a shallow well region of the first conductivity type and a shallow well region of the second conductivity type are formed in the first well forming region, and the shallow well region of the second conductivity type is encompassed by the well region of the first conductivity type, the shallow well region of the first conductivity type formed in the third well forming region, and the buried well region of the first conductivity type in the first well forming region and electrically separated from the semiconductor substrate.
According to the invention, moreover, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming, by patterning, over a major surface of a semiconductor substrate a first mask through which a first well forming region and a second well forming region formed at a distance from the first well forming region are exposed;
(b) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a buried well region of a first conductivity type at a deep position of the semiconductor substrate in the first well forming region;
(c) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a well region of a second conductivity type over the buried well region of the first conductivity type in the first well forming region and the second well forming region;
(d) forming, by patterning, over the major surface of the semiconductor substrate a second mask through which a third well forming region encompassing the buried well region of the first conductivity type of the first well forming region, the shallow well region of the second conductivity type, and a fourth well forming region formed at a distance from the first well forming region are exposed;
(e) doping the semiconductor substrate with an impurity by using the second mask as an impurity introduction mask so as to form a shallow well region of the first conductivity type encompassing the outer periphery of the shallow well region of the second conductivity type of the first well forming region and electrically connected with the buried well region of the first conductivity type of the first well forming region in the third well forming region and to form a shallow well region of the first conductivity type in the fourth well forming region,
wherein when a MIS transistor of a high breakdown voltage is formed in the semiconductor substrate, the shallow well regions other than the shallow well region of high breakdown voltage where the MIS transistor of high breakdown voltage is formed is additionally doped with an impurity of the same conductivity type as that of the other shallow well regions,
wherein in the first well forming region, the shallow well region of the second conductivity type in the first well forming region is encompassed by the shallow well region of the first conductivity type formed in the third well forming region and the buried well region of the first conductivity type in the first well forming region and electrically separated from the semiconductor substrate; and
wherein in the second well forming region, the shallow well region of the second conductivity type is electrically connected with the semiconductor substrate.
According to the invention, moreover, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming, by patterning, over a major surface of a semiconductor substrate a first mask through which a first well forming region and a second well forming region formed at a distance from the first well forming region are exposed;
(b) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a buried well region of a first conductivity type at a deep position of the semiconductor substrate in the first well forming region and the second well forming region;
(c) doping the semiconductor substrate with an impurity by using the first mask as an impurity introduction mask so as to form a well region of a second conductivity type over the buried well region of the first conductivity type in the first well forming region and the well forming region;
(d) forming, by patterning, over the major surface of the semiconductor substrate a second mask through which a third well forming region encompassing the buried well region of the first conductivity type of the first well forming region and the well region of the first well forming region is exposed; and
(e) doping the semiconductor substrate with an impurity by using the second mask as an impurity introduction mask by using the second mask as an impurity introduction mask so as to form a well region of the first conductivity type encompassing the outer periphery of the well region of the second conductivity type of the first well forming region and electrically connected with the buried well region of the first conductivity type of the first well forming region in the third well forming region,
wherein in the first well forming region, the well region of the second conductivity type in the first well forming region is encompassed by the well region of the first conductivity type formed in the third well forming region and the buried well region of the first conductivity type in the first well forming region and electrically separated from the semiconductor substrate,
wherein in the second well forming region, the shallow well region of the second conductivity type is electrically connected with the semiconductor substrate.
Representative summaries of other means will be briefly described in the following.
Specifically, one means comprises:
a buried well region of a first conductivity type formed at a deep position distant from a major surface of a semiconductor substrate in a first well forming region of the semiconductor substrate and in a second well forming region which is formed at a position distance from the first well forming region;
a shallow well region of a second conductivity type formed in self-alignment with the buried well region of the first conductivity type over the buried well region of the first conductivity type in the first well forming region and the second well forming region in such a way that the impurity concentration is set independently of the buried well region of the first conductivity type;
a shallow well region of the first conductivity type encompassing the shallow well region of the second conductivity type of the first well forming region in a third well forming region around the first well forming region and electrically connected with the buried well region of the first conductivity type of the first well forming region; and
a shallow well region of the first conductivity type formed in a fourth well forming region formed at a position distant from any of the first well forming region, the second well forming region, and the third well forming region,
wherein the shallow well region of the second conductivity type of the first well forming region is encompassed by the buried well region of the first conductivity type of the first well forming region and the shallow well region of the first conductivity type of the third well forming region and electrically separated from the semiconductor substrate, and the shallow well region of the second conductivity type of the second well forming region is electrically connected with the semiconductor substrate.
Moreover, another means comprises
a buried well region of a first conductivity type formed at a deep position distant from a major surface of a semiconductor substrate in a first well forming region of the semiconductor substrate and in a second well forming region which is formed at a position distance from the first well forming region;
a shallow well region of a second conductivity type formed in self-alignment with the buried well region of the first conductivity type over the buried well region of the first conductivity type in the first well forming region and the second well forming region in such a way that the impurity concentration is set independently of the buried well region of the first conductivity type; and
a shallow well region of the first conductivity type encompassing the shallow well region of the second conductivity type of the first well forming region in a third well forming region formed around the first well forming region and electrically connected with the buried well region of the first conductivity type of the first well forming region,
wherein the shallow well region of the second conductivity type of the first well forming region is encompassed by the buried well region of the first conductivity type of the first well forming region and the shallow well region of the first conductivity type of the third well forming region and electrically separated from the semiconductor substrate, and the shallow well region of the second conductivity type of the second well forming region is electrically connected with the semiconductor substrate.
In still another means, moreover, the impurity introduction is performed such that the impurity concentration of at least a portion of the shallow well region of the first conductivity type in the third well forming region is higher than that of the shallow well region of the second conductivity type.
In the first well forming region and the second well forming region, moreover, the shallow well regions of the second conductivity type have identical impurity distributions, and the buried well regions of the first conductivity type have identical impurity distributions.